The present invention relates to A/D converters, and more particularly relates to a technique for suppressing degradation of A/D conversion characteristics due to changes in a power supply voltage, a surrounding temperature, properties of a semiconductor device or the like.
FIG. 12 is a block diagram illustrating the configuration of a known A/D converter. The A/D converter of FIG. 12 is a full-flash type A/D converter and includes a reference voltage generator circuit 701, a differential amplifier circuit array 702, a voltage comparator circuit array 703, and an encoder circuit 705.
The reference voltage generator circuit 701 generates a plurality of reference voltages VR1 through VRn+1 by dividing by a plurality (n) of resistors R1 through Rn a voltage between a high voltage side reference voltage applied to a high voltage side terminal 701a and a lower voltage side reference voltage applied to a low voltage side terminal 701b. The generated reference voltages VR1 through VRn+1 are input to the differential amplifier circuit array 702. The differential amplifier circuit array 702 includes n+1 differential amplifier circuits A1 through An+1. Each of the differential amplifier circuits A1 through An+1 amplifies a differential voltage between an analog signal voltage input from an analog voltage input terminal 704 and an associated one of the reference voltages VR1 through VRn+1 to a power supply voltage and then outputs complimentary non-inversion and inversion output voltages, simultaneously with the other ones of the differential amplifier circuits. The voltage comparator circuit array 703 includes n+1 voltage comparator circuits Cr1 through Cr+1. Each of the voltage comparator circuits Cr1 through Cr+1 compares the levels of the non-inversion and inversion output voltages from the associated one of the differential amplifier circuits A1 through An+1 in a previous stage to each other, simultaneously with the other ones of the voltage comparator circuits. The encoder circuit 705 converts n+1 comparison results output from the voltage comparator circuit array 703 and then outputs a single digital data signal having a predetermined resolution.
Compared to various other types of A/D converters such as an integral-mode converter, a serial-parallel converter and a pipeline type converter, the known A/D converter having the above-described parallel structure has the advantage of allowing high-speed A/D conversion. At the same time, however, the known A/D converter has a disadvantage. That is, with the known A/D converter, as the resolution is increased, the differential amplifier circuits and the voltage comparator circuits are increased in number, thus increasing in power consumption and an area of the circuits.
As an A/D converter devised to improve the above-described disadvantage, a technique for dividing an output voltage of a differential amplifier circuit by resistors or the like to interpolate the output voltage is disclosed, for example, in Japanese Laid-Open Patent No. 4-43718. In this technique, respective output voltages from two adjacent differential amplifier circuits are interpolated, and voltage comparison is performed in a voltage comparator circuit using interpolated voltages. Thus, compared to the case where the voltages are not interpolated, the number of differential amplifier circuits can be reduced to a fraction of interpolation bits, so that power consumption and area of an A/D converter can be reduced.
Moreover, conventionally, as an A/D converter of which power consumption is reduced furthermore, an A/D converter using a dynamic voltage comparator circuit as a voltage comparator circuit is disclosed, for example, in Japanese Laid-Open Publication No. 2003-158456. In this technique, instead of a constant current type voltage comparator circuit which is used in a general A/D converter, performs high-speed operation and has excellent responsivity, a dynamic voltage comparator circuit which does not need a constant current is used. Thus, power consumption can be largely reduced.
In recent years, with miniaturization in the semiconductor device fabrication process technology, a power supply voltage is set to be low in many cases. With such a low power supply voltage, an input dynamic range for a plurality of voltage comparator circuits of an A/D converter becomes smaller.
In view of the above-described points, the present inventors examined known A/D converters including the above-described two A/D converters and found the following fact. In a known A/D converter, as an input dynamic range for a voltage comparator circuit is reduced, a margin of an output range for a differential amplifier circuit is reduced. Thus, in the known A/D converter, when changes in semiconductor device fabrication processes represented by change in a threshold voltage of a transistor, a power supply voltage, or a surrounding temperature occur, each of the input dynamic range for a voltage comparator circuit and an output dynamic range for a differential amplifier circuit is changed, so that the input dynamic range and the output dynamic range do not match. This causes the problem of reduction in A/D conversion accuracy.